Job Description

Designs, develops, tests, and debugs software tools, flows, and methodologies used in design automation and by teams in the design of hardware products, process design, or manufacturing. Responsibilities include capturing user stories/requirements, writing both functional and test code, automating build and deployment, and/or performing unit, integration, and end to end testing of the software tools. In this role you will be responsible for developing extraction runsets for one or more of the major EDA vendors on Intel's leading edge process nodes. This includes Synopsys ICV, Siemens Calibre, and Cadence Pegasus. Candidate will work with technology specification owners and validation teams in a coordinated fashion to ensure a high-quality solution.

#DesignEnablement

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Candidate must possess BS degree with 4+ years of experience of MS degree with 3+ years of experience or PhD degree with 1+ years of experience in EE/ECE or related field.

• 3+ years of experience in DRC/LVS runset development in ICV-PXL, or Calibre-SVRF, or Pegasus language.

AND

3+ years of experience in two of the following:

• One of the EDA extraction tools - StarRC/Quantus/Calibre-xACT/xRC

• Scripting in Perl, or Python or TCL.

• CAD/CAE environments that involve circuit simulation or parasitic extraction, or netlisting tools

Preferred Qualifications:

• 3+ years of experience with PDK development

• 3+ years of experience in large scale software development, debugging, and support

• 3+ years of experience in Software development practices such as Agile and Test Driven Development.

• 1+ years IC physical design, layout, and verification flows is highly desired

• 1+ years in IC manufacturing process flows is beneficial

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Other Locations

US, TX, Austin; US, AZ, Phoenix; US, CA, Folsom; US, CA, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

Annual Salary Range for jobs which could be performed in US, California: $123,419.00-$185,123.00

*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.